Disabling portions of memory with defects
US8091000B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2009 |
| Grant date | Jan 3, 2012 |
| Priority date | — |
| Expiry date | Aug 13, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and methods are disclosed herein for identifying and avoiding attempts to access a defective portion of memory. Errors associated with portions of memory, such as a cache memory, are tracked over time enabling detection of both hard and erratic errors. Based on the number of errors tracked over time for a portion of memory, it is determined if the portion of memory is defective. In response to determining portion of memory is defective, the portion of memory is disabled. The portion of memory may be flushed and moved before being disable. Additionally, disabling the portion of memory may be conditioned upon determining if it is allowable to disable the portion of memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.