Method for fabricating vertical channel transistor
US8093122B2 · kind B2 · utility
1Cited by
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15Claims
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Key dates
| Filing date | Jun 27, 2008 |
| Grant date | Jan 10, 2012 |
| Priority date | — |
| Expiry date | May 8, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/63
Abstract
A method for fabricating a vertical channel transistor includes forming a structure including a plurality of trimmed pillar patterns, forming a conductive layer for a gate electrode including a seam over a resultant structure with the pillar patterns, performing an etch-back process until the seam is exposed, and forming a gate electrode by etching the etch-backed conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.