Method of fabricating gate electrode using a hard mask with spacers
US8093146B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 17, 2010 |
| Grant date | Jan 10, 2012 |
| Priority date | — |
| Expiry date | Mar 17, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor device is disclosed. In an embodiment, the method may include providing a semiconductor substrate; forming gate material layers over the semiconductor substrate; forming a hard mask layer over the gate material layers; patterning the hard mask layer to from a hard mask pattern; forming a spacer layer over the hard mask pattern; etching back the spacer layer to form spacers over sidewalls of the hard mask pattern; etching the gate material layers by using the spacers and the hard mask pattern as an etching mask to form a gate structure; and performing a tilt-angle ion implantation process to the semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.