Chemical-mechanical polish termination layer to build electrical device isolation
US8093576B1 · kind B1 · utility
17Cited by
1References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 30, 2009 |
| Grant date | Jan 10, 2012 |
| Priority date | — |
| Expiry date | Jan 19, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/826
Abstract
A method of forming a semiconductor device may comprise forming a memory portion, forming a carbon film, depositing insulation to at least partially cover the carbon film, and terminating patterned removal of the insulation at the carbon film during a fabrication process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.