Flip chip semiconductor package and fabrication method thereof
US8093721B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2007 |
| Grant date | Jan 10, 2012 |
| Priority date | — |
| Expiry date | Jun 13, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There is provide a flip chip semiconductor package comprising: an electrode pad formed a semiconductor substrate; a lower metal bonding layer formed on the electrode pad; an upper metal bonding layer formed on the lower metal bonding layer and having a post shape of a predetermined height; and a conductive bump formed on the upper metal bonding layer, and a solder bump covers at least partially the surface of the upper metal bonding layer. An insulating layer for electrode reconfiguration is formed around the electrode pad on the substrate, and the insulating layer has a predetermined thickness to prevent the penetration of α particles from the solder bump. The semiconductor package may further comprise an oxidation preventing layer between the solder bump and the upper metal bonding layer. In accordance with the present invention, there is realized the flip chip semiconductor package which improves the adhesive strength of the solder bump and which more improves the reliability in the flip chip bump structure of fine pitches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.