Method of fast tracking and jitter improvement in asynchronous sample rate conversion
US8093933B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2009 |
| Grant date | Jan 10, 2012 |
| Priority date | — |
| Expiry date | Sep 18, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/0628
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for fast tracking and jitter improvement in an asynchronous sample rate conversion includes a digital phase locked loop (DPLL) for an asynchronous sample rate conversion (ASRC) device. A control apparatus in the DPLL includes a gain controller that sets and maintains gains (Ki, Kp) of two branches of the control apparatus at a fixed value, which enables searching of a desired value by the DPLL to determine a neighborhood of the desired value, and reduces the gains when the number of samples reaches a predetermined number. Processing units in the DPLL generate and process first and second input signals based on an input clock, an output clock, and a system clock. The second input signal is processed using two branches. Signals resulting from the two branches are re-aligned according to a changed status of the first processed input signal such that the signals resulting from the two branches are sampled in the same input clock interval.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.