Phase-locked loop system with a phase-error spreading circuit
US8094769B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2008 |
| Grant date | Jan 10, 2012 |
| Priority date | — |
| Expiry date | Aug 4, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase-locked loop (PLL) system including a phase-frequency detector for generating an up signal or a down signal based on a phase difference between a reference clock and a feedback clock is provided. The PLL system further includes a phase-error spreading circuit for generating phase-spread pulses based on a relationship between a first time attribute of the up signal or the down signal and a second time attribute of the phase-spread pulses. The PLL system further includes a voltage-controlled oscillator (VCO) for generating a VCO clock based on the phase-spread pulses. The PLL system may also include a charge pump that generates a pumping signal based on the phase-spread pulses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.