Patent · US Active

Transaction based verification of a system on chip on system level by translating transactions into machine code

US8095331B2 · kind B2 · utility

2Cited by

2References

28Claims

0Family size

Assignee

GlobalFoundries Inc. · KY

Inventors

Christian Haufe · Dresden, DE
Ingo Kuehn · Wettingen, CH
David Larsen · San Jose, US

Key dates

Filing date	Nov 26, 2008
Grant date	Jan 10, 2012
Priority date	—
Expiry date	Mar 10, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06F11/2236
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In a transaction-based verification environment for complex semiconductor devices, enhanced verification efficiency may be achieved by providing a transaction to machine code translator and an appropriate interface that enables access of the translated machine code instruction by a CPU under test. In this manner, transaction-based test environments may have a high degree of re-usability and may be used for verification on block level and system level.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.