Managing cache line allocations for multiple issue processors
US8095734B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2009 |
| Grant date | Jan 10, 2012 |
| Priority date | — |
| Expiry date | Jul 20, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0864
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus having a cache configured as N-way associative and a controller circuit is disclosed. The controller circuit may be configured to (i) detect one of a cache hit and a cache miss in response to each of a plurality of access requests to the cache, (ii) detect a collision among the access requests, (iii) queue at least two first requests of the access requests that establish a speculative collision, the speculative collision occurring where the first requests access a given congruence class in the cache and (iv) delay a line allocation to the cache caused by a cache miss of a given one of the first requests while the given congruence class has at least N outstanding line fills in progress.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.