Error management firewall in a multiprocessor computer
US8095759B2 · kind B2 · utility
2Cited by
0References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 29, 2009 |
| Grant date | Jan 10, 2012 |
| Priority date | — |
| Expiry date | Jul 10, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L63/0227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessor computer system comprises a plurality of processors and a plurality of nodes, each node comprising one or more processors. A local memory in each of the plurality of nodes is coupled to the processors in each node, and a hardware firewall comprising a part of one or more of the nodes is operable to prevent a write from an unauthorized processor from writing to the local memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.