Sensor device with reduced parasitic-induced error
US8096179B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 9, 2009 |
| Grant date | Jan 17, 2012 |
| Priority date | — |
| Expiry date | Jul 29, 2030 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81B3/0086
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A device (110) includes a sensing element (26) having drive nodes (34, 36) and sense nodes (42, 44). Parasitic capacitance (22) is present between drive node (34) and sense node (42). Likewise, parasitic capacitance (24) is present between drive node (36) and sense node (44). When a drive signal (56) is applied between drive nodes (34, 36), a parasitic current (70) between drive and sense nodes (34, 42) and a parasitic current (72) between drive and sense nodes (36,44) is created due to the parasitic capacitances (22, 24). A capacitive network (112) is coupled between the drive node (36) and the sense node (42) to create a correction current (134) through capacitive network (112) that cancels parasitic current (70). Likewise, a capacitive network (114) is coupled between the drive node (34) and the sense node (44) to create a correction current (138) through capacitive network (112) that cancels parasitic current (72).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.