Control of localized air gap formation in an interconnect stack
US8097949B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 21, 2007 |
| Grant date | Jan 17, 2012 |
| Priority date | — |
| Expiry date | Mar 12, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a method for fabricating an interconnect stack of an integrated-circuit device. Air gaps are fabricated in the interconnect stack on one or more interconnect levels. The method comprises forming local etch vias (216, 218) between a lower etch-barrier layer (236) and an upper etch-barrier layer (211) on top of an upper-intermediate interconnect level (224). Lateral inhomogeneities of the dielectric constant on the upper-intermediate interconnect level are removed in comparison with prior-art devices. For in the finished interconnect stack local variations in the dielectric permittivity can only occur at the (former) etch vias, which are either visible by the presence of air cavities or hardly visible due to a later filling with the dielectric material of the next interlevel dielectric layer. The integrated-circuit device of the invention completely avoids a penetration of copper from the metal interconnect line sections into the adjacent interlevel or intermetal dielectric layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.