Push for sharing instruction
US8099557B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2008 |
| Grant date | Jan 17, 2012 |
| Priority date | — |
| Expiry date | Nov 7, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a system comprises a first processor, a main memory system, and a cache hierarchy coupled between the first processor and the main memory system. The cache hierarchy comprises at least a first cache. The first processor is configured to execute a first instruction, including forming an address responsive to one or more operands of the first instruction. The system is configured to push a first cache block that is hit by the first address in the first cache to a target location within the cache hierarchy or the main memory system, wherein the target location is unspecified in a definition of the first instruction within an instruction set architecture implemented by the first processor, and wherein the target location is implementation-dependent.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.