System and method for generating fast instruction and data interrupts for processor design verification and validation
US8099559B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2007 |
| Grant date | Jan 17, 2012 |
| Priority date | — |
| Expiry date | Nov 16, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/683
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for intentionally invaliding translation entry valid bits in order to provoke storage interrupts when executing a test case is presented. Prior to executing the test case, an interrupt handler pseudo-randomly invalidates a number of translation entries included in a translation lookaside buffer (TLB) by changing particular valid bits in order to provoke initial storage interrupts, such as an instruction storage interrupt (ISI) or a data storage interrupt (DSI). Once the processor executes the test case that, in turn, triggers a storage interrupt, the interrupt handler uses an index counter to validate particular valid bits and invalidate other valid bits, thus provoking subsequent storage interrupts. In one embodiment, the interrupt handler also changes valid bits in a page table when the processor executes in a mode that accesses the page table in addition to the TLB.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.