Scalable interface for a memory array
US8099562B2 · kind B2 · utility
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16Claims
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Key dates
| Filing date | Jan 8, 2008 |
| Grant date | Jan 17, 2012 |
| Priority date | — |
| Expiry date | Nov 4, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/126
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for accessing a memory array includes receiving, from multiple requesters, memory access requests directed to a single port of the memory array. The memory access requests associated with each of the multiple requesters are serviced, based on a priority assigned to each of the multiple requesters, while maintaining a fixed timing for the memory access requests.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.