Error correcting Viterbi decoder
US8099657B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 2008 |
| Grant date | Jan 17, 2012 |
| Priority date | — |
| Expiry date | Nov 16, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0052
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and corresponding systems in a Viterbi decoder include selecting an input symbol in an input block, wherein the input block has a plurality of input symbols, wherein each input symbol has a Boolean value, a quality value, and an associated stage, and wherein the selected symbol is selected based upon the quality value of the selected symbol relative to a quality value of other input symbols in the input block. Thereafter, the Boolean value of the selected symbol is complemented to produce a complemented symbol. The complemented symbol is substituted for the selected symbol to produce an alternate input block. A Viterbi algorithm is executed using the alternate input block to produce an alternate decoded bit sequence, which is then checked for errors using an error check. The alternate decoded bit sequence is output in response to the alternate decoded bit sequence passing the error check.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.