Semiconductor device and manufacturing method of the same
US8101433B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2009 |
| Grant date | Jan 24, 2012 |
| Priority date | — |
| Expiry date | Oct 14, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.