Chip package structure and method for fabricating the same
US8102058B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2010 |
| Grant date | Jan 24, 2012 |
| Priority date | — |
| Expiry date | Sep 28, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The disclosure provides a chip package structure and method for fabricating the same. The chip package structure includes at least one chip having at least one through via. At least one stress buffering structure is disposed in the through via. The stress buffering structure includes a first gasket and a second gasket. A supporting pillar has two terminals respectively connected to the first gasket and the second gasket. The cross-sectional area of the supporting pillar is smaller than areas of the first gasket and the second gasket. A buffering layer is sandwiched between the first gasket and the second gasket, surrounding a sidewall of the supporting pillar. An insulating layer is disposed on the through via, surrounding a sidewall of the stress buffering structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.