Electrostatic discharge power clamp trigger circuit using low stress voltage devices

US8102632B2 · kind B2 · utility

Assignee

• Advanced Micro Devices, Inc. · US

Inventors

• Yikai Liang · Fremont, US
• Arvind Bomdica · Palo Alto, US
• Samudyatha Suryanarayana · Sunnyvale, US
• Gayatri Gopalan · Sunnyvale, US
• Min Xu · Lo Wu, CN
• Xin Peng Liu · Beijing, CN
• Ming-Ju Edward Lee · San Jose, US

Key dates

• Filing date: Mar 18, 2009
• Grant date: Jan 24, 2012
• Expiry date: Apr 21, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K19/00315
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of the IC includes a voltage drop network and a plurality of shunt circuits to protect the IC against excessive supply voltages and ESD voltages. Each shunt circuit includes an RC trigger stage and an NMOS shunt stage that are made using low-voltage devices. A protection circuit of the embodiments includes a high voltage IO pin interface, a voltage drop network coupled to the IO pin and comprising a plurality of forward-biased diodes connected in series to drop a high voltage on the IO pin to a low voltage level, an NMOS shunt transistor coupled between the voltage drop network and a ground terminal, and a trigger circuit coupled to the NMOS shunt transistor to activate the shunt transistor when a sensed input voltage rise time is shorter than a defined supply voltage rise time.