Disabling cache portions during low voltage operations
US8103830B2 · kind B2 · utility
8Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2008 |
| Grant date | Jan 24, 2012 |
| Priority date | — |
| Expiry date | Jun 25, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.