Cache memory and a method for servicing access requests
US8103833B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2007 |
| Grant date | Jan 24, 2012 |
| Priority date | — |
| Expiry date | May 27, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1012
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache memory that includes: (i) an arbitrator, connected to multiple access generator, the arbitrator is adapted to receive different types of access requests from the multiple access generators and to select a single access request per arbitration cycle; (ii) a sequence of pipeline stages, the sequence comprises an input pipeline stage that is connected to the arbiter; and (iii) multiple cache resources, connected to the sequence of pipeline stages; wherein each cache resource can be read only by a small portion of the sequence of pipeline stages and can be written to only by a small portion of the sequence of pipeline stages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.