Method and apparatus for power savings in a multi-threaded processor using a symbol gated with a clock signal
US8103888B2 · kind B2 · utility
1Cited by
5References
20Claims
0Family size
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Key dates
| Filing date | Nov 26, 2008 |
| Grant date | Jan 24, 2012 |
| Priority date | — |
| Expiry date | Mar 29, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses are presented that allow power savings on a processor executing a plurality of threads on a plurality of cores. The method may include providing a first timing signal to a processor, determining the power requirements of the processor, loading a symbol into a shift register, where the symbol may be associated with the power requirements of the processor, providing a second timing signal to the processor, where the second timing signal may include a gated representation of the first timing signal and the symbol.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.