Apparatus and methods for optimizing the performance of programmable logic devices using multiple supply voltage
US8103975B2 · kind B2 · utility
9Cited by
26References
9Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 1, 2008 |
| Grant date | Jan 24, 2012 |
| Priority date | — |
| Expiry date | Jul 29, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17784
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable logic device (PLD) includes first and second circuits. The first and second circuits are part of a user's design to be implemented using the PLD's resources. The first circuit is powered by a first supply voltage. The second circuit is powered by a second supply voltage. At least one of the first and second supply voltages is determined by a PLD computer-aided design (CAD) flow used to implement the user's design in the PLD.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.