Patent · US Active

Method and apparatus for thermal analysis of through-silicon via (TSV)

US8103996B2 · kind B2 · utility

12Cited by

5References

38Claims

0Family size

Assignee

Cadence Design Systems, Inc. · US

Inventors

Vinod Kariat · Sunnyvale, US
Eddy Pramono · Santa Clara, US
Yong Zhan · Milpitas, US

Key dates

Filing date	Apr 1, 2009
Grant date	Jan 24, 2012
Priority date	—
Expiry date	Jun 11, 2029

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/08
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout. The IC design layout includes several wiring layers in some embodiments. The IC design layout includes a substrate that has at least one through-silicon via (“TSV”). The method divides the IC design layout into a set of elements. The method identifies a temperature distribution for the IC design layout by using the set of elements. In some embodiments, at least one element includes a metal component and a non-metal component. The non-metal component is silicon in some embodiments, and a dielectric in other embodiments.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.