System and methods for reducing clock power in integrated circuits

US8104012B1 · kind B1 · utility

Assignee

• XILINX, INC. · US

Inventors

• Matthew H. Klein · Redwood City, US
• Edward S. McGettigan · San Jose, US
• Stephen M. Trimberger · San Jose, US
• James M. Simkins · Park City, US
• Brian D. Philofsky · Longmont, US
• Subodh Gupta · Calgary, CA

Key dates

• Filing date: Jan 31, 2009
• Grant date: Jan 24, 2012
• Expiry date: Dec 1, 2029

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2117/04
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Dynamic power savings and efficient use of resources are achieved in a programmable logic device (PLD) such as a field programmable gate array (FPGA) or complex programmable logic device (CPLD) by receiving a design netlist specifying a circuit including clock signals, clock buffers, clock enable signals and synchronous elements, examining the design netlist to identify synchronous elements coupled to common clock and clock enable signals, cutting the clock signals to the synchronous elements to form a modified design netlist, inserting gated clock buffers into the modified netlist to output gated clock signals to the synchronous elements, responsive to the clock enable signals, and performing placement and routing on the modified netlist. A system for performing the method on an EDA tool is provided. The methods may be provided as executable instructions stored on a computer readable medium which cause a programmable processor to perform the methods.