Inducing stress in CMOS device

US8105887B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Zhijiong Luo · Poughkeepsie, US
• Qingqing Liang · Fishkill, US
• Haizhou Yin · Poughkeepsie, US
• Huilong Zhu · Poughkeepsie, US

Key dates

• Filing date: Jul 9, 2009
• Grant date: Jan 31, 2012
• Expiry date: Jul 20, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/201

Abstract

A first aspect of the invention provides a method of forming a semiconductor device, the method comprising: providing a complimentary metal oxide semiconductor (CMOS) device including: a silicon substrate layer; a silicon dioxide layer thereover; and an n-type field effect transistor (NFET) gate having a first recessed source/drain trench and a p-type field effect transistor (PFET) gate having a second recessed source/drain trench, the NFET gate and the PFET gate located over the silicon dioxide layer; depositing a nitride stress liner in the first recessed source/drain trench and the second recessed source/drain trench; depositing an oxide layer over the nitride stress liner; placing the CMOS device on a handling wafer, wherein the oxide layer is closest to the handling wafer; removing the silicon substrate layer; etching the silicon dioxide layer to form an opening abutting a portion of a source/drain region, the source/drain region abutting one of the first recessed source/drain trench or the second recessed source/drain trench; and forming a contact in the opening.