Semiconductor die with fuse window and a monitoring window over a structure which indicates fuse integrity
US8106476B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2007 |
| Grant date | Jan 31, 2012 |
| Priority date | — |
| Expiry date | Jul 17, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to one exemplary embodiment, a method for monitoring structural integrity of at least one fuse in semiconductor wafer, which includes at least one electrical monitoring structure, includes forming a monitoring window in a dielectric layer overlying the at least one electrical monitoring structure, where the monitoring window and a fuse window overlying the at least one fuse are, in one embodiment, formed in a same etch process. The method further includes performing at least one electrical measurement on the at least one electrical monitoring structure, wherein the at least one electrical measurement is utilized to monitor the structural integrity of the at least one fuse. A change in the at least one electrical measurement is utilized to indicate a change in the structural integrity of the at least one fuse. The at least one electrical monitoring structure can include, for example, a metal serpentine line and one or more metal combs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.