Integrated circuit package and packaging method
US8106489B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2008 |
| Grant date | Jan 31, 2012 |
| Priority date | — |
| Expiry date | Aug 14, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A package and packaging method are provided that enable packaging of larger dies and/or smaller packages. Generally, the method includes steps of: (i) reducing a thickness of a portion of a top surface of leads of a leadframe extending into a package being formed; (ii) mounting a die to a paddle of the leadframe, the die extending past an edge of the paddle into a space created by reducing the thickness of the leads; and (iii) encapsulating the die and leadframe, including the reduced portion of the leads, in a molding compound. In one embodiment, the leads are reduced by half-etching the portion of the top surface. Preferably, the method further includes wire bonding pads on the die to etched portions of the leads to electrically couple the die to the leads. Alternatively, wire bonding is between the pads and non-etched portions of the leads. Other embodiments are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.