Semiconductor package and manufacturing method thereof
US8106492B2 · kind B2 · utility
13Cited by
115References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2009 |
| Grant date | Jan 31, 2012 |
| Priority date | — |
| Expiry date | Dec 16, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The advanced quad flat non-leaded package structure includes a carrier having a die pad and a plurality of leads, at least a chip, a plurality of wires, and a molding compound. The rough surface of the carrier enhances the adhesion between the carrier and the surrounding molding compound.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.