Patent · US Active

Reduced-stress through-chip feature and method of making the same

US8106511B2 · kind B2 · utility

0Cited by

4References

24Claims

0Family size

Assignee

Qimonda AG · DE

Inventors

Harry Hedler · Germering, DE
Roland Irsigler · Munich, DE
Rolf Weis · Dresden, DE
Detlef Weber · Grünberg, DE

Key dates

Filing date	Feb 28, 2008
Grant date	Jan 31, 2012
Priority date	—
Expiry date	Sep 17, 2029

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/0002
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A feature is inscribed in a major surface of a microelectronic workpiece having a material property expressed as a reference coefficient value. The feature includes a first material having a first coefficient value for the material property and a second material having a second coefficient value for the material property. The first coefficient value is different from the reference coefficient value different from the first coefficient value and the second coefficient value is different from the first coefficient value. The first and second materials behave as an aggregate having an aggregate coefficient value for the material property between the first coefficient value and the reference coefficient value.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.