Patent · US Active

Copper damascene and dual damascene interconnect wiring

US8106513B2 · kind B2 · utility

5Cited by
5References
17Claims
0Family size

Assignee

Inventors

Key dates

Filing dateNov 9, 2009
Grant dateJan 31, 2012
Priority date
Expiry dateDec 20, 2029

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L21/76834
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A copper corrosion resistant integrated circuit. The integrated circuit including: a substrate; a copper diffusion barrier layer on the substrate; a dielectric layer on a top surface of the copper diffusion barrier layer; a copper damascene or dual damascene wire in the dielectric layer, a top surface of the copper damascene or dual damascene wire coplanar with a top surface of the dielectric layer; a first capping layer on the top surface of the wire and the top surface of the dielectric layer; and a second capping layer on a top surface of the first capping layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.