Word line voltage control in STT-MRAM
US8107280B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2008 |
| Grant date | Jan 31, 2012 |
| Priority date | — |
| Expiry date | May 18, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/1675
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, circuits and methods for controlling the word line voltage applied to word line transistors in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. One embodiment is directed to a STT-MRAM including a bit cell having a magnetic tunnel junction (MTJ) and a word line transistor. The bit cell is coupled to a bit line and a source line. A word line driver is coupled to a gate of the word line transistor. The word line driver is configured to provide a word line voltage greater than a supply voltage below a transition voltage of the supply voltage and to provide a voltage less than the supply voltage for supply voltages above the transition voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.