Optimized FFT/IFFT module
US8107357B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 26, 2007 |
| Grant date | Jan 31, 2012 |
| Priority date | — |
| Expiry date | Nov 29, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/2651
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
We disclose an optimal hardware implementation of the FFT/IFFT operation that minimizes the number of clock cycles required to compute the FFT/IFFT while at the same time minimizing the number of complex multipliers needed. An input module combines a plurality of inputs after applying a multiplication factor to each of the inputs. At least one multiplicand generator generates multiplicands. At least two complex multiplier modules perform complex multiplications with at least one of the complex multiplier modules receiving an output from the input module. A map module receives outputs of the at least two complex multiplier modules, the map module selecting and applying a multiplication factor to each of the outputs received to generate multiple outputs. Finally, an accumulation module receives and performs an accumulation task on each of the multiple outputs of the map module thereby generating a corresponding number of multiple outputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.