Cache-based control of atomic operations in conjunction with an external ALU block
US8108610B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 2008 |
| Grant date | Jan 31, 2012 |
| Priority date | — |
| Expiry date | Nov 9, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/253
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the invention sets forth a mechanism for efficiently processing atomic operations transmitted from multiple general processing clusters to an L2 cache. A tag look-up unit tracks the availability of each cache line in the L2 cache, reserves the necessary cache lines for the atomic operations and transmits the atomic operations to an ALU for processing. The tag look-up unit also increments a reference counter associated with a reserved cache line each time an atomic operation associated with that cache line is received. This feature allows multiple atomic operations associated with the same cache line to be pipelined to the ALU. A ROP unit that includes the ALU may request additional data necessary to process an atomic operation from the L2 cache. Result data is stored in the L2 cache and may also be returned to the general processing clusters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.