Semiconductor memory chip and memory system

US8108643B2 · kind B2 · utility

Assignee

• Qimonda AG · DE

Inventors

• Paul Wallner · Prien am Chiemsee, DE
• Peter Gregorius · Munich, DE

Key dates

• Filing date: Jul 29, 2005
• Grant date: Jan 31, 2012
• Expiry date: Oct 13, 2027

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C7/10
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

In a semiconductor memory system having a loop forward architecture, the command, address and write data stream and the separate read data stream in form of protocol-based frames transmitted to/from memory chips in the following order: memory controller to the first memory chip, to the second memory chip, to the third memory chip and to the fourth memory chip and the read data stream is transferred from the fourth memory chip to the memory controller. With each command usually one of four memory chips is accessed for data processing, while three of four memory chips have only to fulfil a simple re-drive of CAwD stream and read data stream. By separately transferring a rank select signal not embedded in the frame from the memory controller to each memory chip a lot of more flexibility for these tasks can be achieved. Each memory chip includes a rank select switching section receiving the separately transferred rank select signal and decoding therefrom signal states which are used to select whether a CAwD signal stream is to be sent to the own memory core and processed or re-driven to the next memory chip and whether a read data stream is to be taken from its own memory core or from …