Optimizing the size of memory devices used for error correction code storage
US8108761B2 · kind B2 · utility
1Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2007 |
| Grant date | Jan 31, 2012 |
| Priority date | — |
| Expiry date | Oct 30, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, methods, and apparatuses for optimizing the size of memory devices used for error correction code storage. An apparatus (such as a memory module) may include a number of memory devices to store data and a memory device to store error correction (ECC) bits. The memory devices to store data may have a density of N and the memory device to store ECC bits has a density of ½ N.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.