Operating method and circuit for low density parity check (LDPC) decoder
US8108762B2 · kind B2 · utility
5Cited by
5References
14Claims
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Key dates
| Filing date | Nov 13, 2007 |
| Grant date | Jan 31, 2012 |
| Priority date | — |
| Expiry date | Nov 30, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6591
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An operating method and a circuit for low density parity check (LDPC) decoders, in which original bit nodes are incorporated into check nodes for simultaneous operation. The bit node messages are generated according to the difference between the newly generated check messages and the previous check node messages. The bit node messages can be updated immediately, and the decoder throughput can be improved. The required memory of LDPC decoders can be effectively reduced, and the decoding speed can also be enhanced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.