Modifying an operation of one or more processors executing message passing interface tasks
US8108876B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2007 |
| Grant date | Jan 31, 2012 |
| Priority date | — |
| Expiry date | Oct 2, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/509
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Mechanisms for modifying an operation of one or more processors executing message passing interface (MPI) tasks are provided. Mechanisms for adjusting the balance of processing work loads of the processors are provided so as to minimize wait periods for waiting for all of the processors to call a synchronization operation. Each processor has an associated hardware implemented MPI load balancing controller. The MPI Load balancing controller maintains a history that provides a profile of the tasks with regard to their calls to synchronization operations. From this information, it can be determined which processors should have their processing loads lightened and which processors are able to handle additional processing loads without significantly negatively affecting the overall operation of the parallel execution system. As a result, operations may be performed to shift workloads from the slowest processor to one or more of the faster processors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.