Integrated circuit wafer system with control strategy
US8110412B2 · kind B2 · utility
2Cited by
4References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2006 |
| Grant date | Feb 7, 2012 |
| Priority date | — |
| Expiry date | Dec 22, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/12
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit wafer system includes an integrated circuit wafer, measuring thicknesses of the integrated circuit wafer, calculating a change in temperature ramp rates and thickness offsets for subsequent processing based on the temperature ramp rates for prior processing and the resultant thicknesses, and calculating an average temperature and deposition time for subsequent processing based on calculated changes in temperature ramp rates, coupled with the average temperature, deposition time for prior processing, and the resultant thicknesses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.