Forming integrated circuit devices with metal-insulator-metal capacitors using selective etch of top electrodes

US8110414B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Marshall O. Cathey, Jr. · Denison, US
• Pushpa Mahalingam · Richardson, US
• Weidong Tian · Dallas, US
• David C. Guiling · Naples, US
• Xinfen Chen · Plano, US
• Binghua Hu · Plano, US
• Sopa Chevacharoenkul · Richardson, US

Key dates

• Filing date: Apr 30, 2009
• Grant date: Feb 7, 2012
• Expiry date: Jan 2, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L22/26
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of forming integrated circuits (IC) having at least one metal insulator metal (MIM) capacitor. A bottom electrode is formed on a predetermined region of a semiconductor surface of a substrate. At least one dielectric layer including silicon is formed on the bottom electrode, wherein a thickness of the dielectric layer is <1,000 A. A top electrode layer is formed on the dielectric layer. A patterned masking layer is formed on the top electrode layer. Etching using dry-etching at least in part is used to etch the top electrode layer outside the patterned masking layer to reach the dielectric layer, which removes ≦100 A of the thickness of the dielectric layer. The dry etch process includes using a first halogen comprising gas, a second halogen comprising gas that comprises fluorine, and a carrier gas.