Patent · US Active

Method of making and designing lead frames for semiconductor packages

US8110447B2 · kind B2 · utility

0Cited by

5References

7Claims

0Family size

Assignee

FAIRCHILD SEMICONDUCTOR CORPORATION · US

Inventors

Lay Yeap Lim · Bukit Mertajam, MY
David Chong · Bukit Mertajam, MY

Key dates

Filing date	Mar 21, 2008
Grant date	Feb 7, 2012
Priority date	—
Expiry date	May 21, 2029

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/181
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A lead frame with patterned conductive runs on the top surface to accept a wire bonded or flip-chip or COL configuration is disclosed. The top pattern is completed and the bottom is etched away creating cavities. The cavities are filled with a pre-mold material that lend structural support of the lead frame. The top is then etch through the lead frame to the pre-mold, except with the top conductive runs exist. In this manner the conductive runs are completed and isolated from each other so that the placement of the runs is flexible. The chips are mounted and the encapsulated and the lead frames are singulated. The pattern on the top and the bottom may be defined by first plated the patterns desired.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.