Cross OD FinFET patterning
US8110466B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2010 |
| Grant date | Feb 7, 2012 |
| Priority date | — |
| Expiry date | Jul 26, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/011
Abstract
A method of forming an integrated circuit structure includes providing a semiconductor substrate; providing a first lithography mask, a second lithography mask, and a third lithography mask; forming a first mask layer over the semiconductor substrate, wherein a pattern of the first mask layer is defined using the first lithography mask; performing a first etch to the semiconductor substrate to define an active region using the first mask layer; forming a second mask layer having a plurality of mask strips over the semiconductor substrate and over the active region; forming a third mask layer over the second mask layer, wherein a middle portion of the plurality of mask strips is exposed through an opening in the third mask layer, and end portions of the plurality of mask strips are covered by the third mask layer; and performing a second etch to the semiconductor substrate through the opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.