Method of manufacturing semiconductor wafer by forming a strain relaxation SiGe layer on an insulating layer of SOI wafer
US8110486B2 · kind B2 · utility
8Cited by
4References
3Claims
0Family size
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Key dates
| Filing date | Jan 5, 2007 |
| Grant date | Feb 7, 2012 |
| Priority date | — |
| Expiry date | Jan 5, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0262
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor wafer is produced at a step of forming a lattice relaxation or a partly lattice-relaxed strain relaxation SiGe layer on an insulating layer in a SOI wafer comprising an insulating layer and a SOI layer, wherein at least an upper layer side portion of the SiGe layer is formed on the SOI layer at a gradient of Ge concentration gradually decreasing toward the surface and then subjected to a heat treatment in an oxidizing atmosphere.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.