Real time process monitoring and control for semiconductor junctions
US8110828B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2011 |
| Grant date | Feb 7, 2012 |
| Priority date | — |
| Expiry date | Jun 9, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
Abstract
A method of manufacturing a semiconductor layer is provided. In a first deposition during a first period of time, at least one Group IIIA element and at least one Group VIA element are deposited on a substrate or on a layer optional disposed on the substrate such as a back-electrode. During a second deposition during a second period of time, at least one Group IB element and the at least one group VIA element are deposited on the substrate or the optional layer. The one Group IB element combines with the Group VIA element to form a IB2VIA composition. A first deposition state is monitored, during the second deposition by making a first plurality of measurements of a first deposition state. The second deposition is terminated or attenuated based on a function of the first plurality of measurements of the indicia of the first deposition state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.