Patent · US Active

Building block for a secure CMOS logic cell library

US8111089B2 · kind B2 · utility

26Cited by

35References

19Claims

0Family size

Assignees

Inventors

Ronald P. Cocchi · Henry's Drive, US
James P. Baukus · Westlake Village, US
Bryan J. Wang · South Lake Tahoe, US
Lap-Wai Chow · La Cañada Flintridge, US
Paul Ouyang · Shanghai, CN

Key dates

Filing date	May 24, 2010
Grant date	Feb 7, 2012
Priority date	—
Expiry date	May 24, 2030

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/20
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A logical building block and method of using the building block to design a logic cell library for CMOS (Complementary Metal Oxide Silicon) ASICs (Application Specific Integrated Circuits) is disclosed. Different logic gates, built with the same building block as described in this invention, will have the same schematics of transistor connection and also the same physical layout so that they appear to be physically identical under optical or electron microscopy. An ASIC designed from a library of such logic cells is strongly resistant to a reverse engineering attempt.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.