Field programmable gate array
US8112466B2 · kind B2 · utility
15Cited by
3References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2005 |
| Grant date | Feb 7, 2012 |
| Priority date | — |
| Expiry date | Jun 18, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An efficient implementation of DSP functions in a field programmable gate array (FPGA) using one or more computational blocks, each block having of a multiplier, an accumulator, and multiplexers. The structure implements most common DSP equations in a fast and a highly compact manner. A novel method for cascading these blocks with the help of dedicated DSP lines is provided, which leads to a very simple and proficient implementation of n-stage MAC operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.