Addressing scheme to allow flexible mapping of functions in a programmable logic array
US8112551B2 · kind B2 · utility
9Cited by
2References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 7, 2010 |
| Grant date | Feb 7, 2012 |
| Priority date | — |
| Expiry date | Oct 7, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/109
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable processing device comprises a plurality of universal digital blocks (UDBs) in a UDB linear array. Each register in each UDB is associated with a plurality of memory addresses, where each memory address is from each of the different memory address spaces associated with different access mode widths of different digital peripheral functions. A digital peripheral function of an access mode width is mapped to one or more contiguous UDBs starting with a first UDB in the UDB linear array. Based on the access mode width, one of the associated memory addresses is chosen for the first UDB.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.