Arrangement comprising a first semiconductor chip and a second semiconductor chip connected thereto

US8112563B2 · kind B2 · utility

Assignees

• Infineon Technologies AG · DE
• Robert Bosch GmbH · DE

Inventors

• Jens Barrenscheen · Munich, DE
• Peter Rohm · Brackenheim, DE
• Hannes Estl · Klagenfurt, AT
• Axel Aue · Strohberg, DE
• Jens Graf · Gochsheim, DE
• Herman Roozenbeek · Schwieberdingen, DE

Key dates

• Filing date: Dec 2, 2003
• Grant date: Feb 7, 2012
• Expiry date: Dec 26, 2026

Classification

• Technology area (CPC G): Physics
• CPC primary: G05B2219/25012
• WIPO field: Control
• WIPO sector: Instruments

Abstract

An arrangement including a first semiconductor chip and a second semiconductor chip connected thereto, where the second semiconductor chip is additionally connected to electrical loads and drives these electrical loads on the basis of a timing which is prescribed to it by load control data, and where the first semiconductor chip transmits to the second semiconductor chip the aforementioned load control data and pilot data which control the second semiconductor chip, and where the second semiconductor chip transmits to the first semiconductor chip diagnostic data which represent states prevailing in the second semiconductor chip or events which occur. The diagnostic data are transmitted via a first transmission channel and the load control data and the pilot data are transmitted via a second transmission channel.