Enhanced control of CPU parking and thread rescheduling for maximizing the benefits of low-power state
US8112648B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2008 |
| Grant date | Feb 7, 2012 |
| Priority date | — |
| Expiry date | Sep 28, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system may comprise a plurality of processing units and a scheduler configured to maintain a record for each respective processing unit. Each respective record may comprise entries which may indicate 1) how long the respective processing unit has been residing in an idle state, 2) a present power-state in which the respective processing unit resides, and 3) whether the respective processing unit is a designated default (bootstrap) processing unit. The scheduler may select one or more of the plurality of processing units according to their respective records, and assign impending instructions to be executed on the selected one or more processing units. Where additional processing units are required, the scheduler may also insert an instruction to trigger an inter-processor interrupt to transition one or more processing units out of idle-state. The scheduler may then assign some impending instructions to these one or more processing units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.