Method and device for bad-block testing
US8112682B2 · kind B2 · utility
3Cited by
5References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 23, 2009 |
| Grant date | Feb 7, 2012 |
| Priority date | — |
| Expiry date | Dec 31, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus and methods for effecting bad-block testing operations are disclosed herein. In some embodiments, instead of effecting bad-block testing for the majority of the flash memory blocks of a flash memory device during manufacture, most or all bad-block testing is postponed until the end user is in possession of the flash memory device. In some embodiments, after user data is received by the flash memory device from a host device, one or more blocks of the flash memory device are subjected to bad-block testing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.